3236 scott boulevard santa clara, california 95054 phone: (408) 986-5060 fax: (408) 986-5095 CMM3566-LC features ? 7.0v bias voltage ? +24 dbm linear output power (w-cdma) ? 30 db gain at operating output ? tested under digital modulation (w-cdma) ? leadless chip carrier (lcc) package applications ? wireless local loop subscriber units ? wireless local loop base stations description the CMM3566-LC is a 7.0 v, +24 dbm, linear power amplifier intended for use in pcs handsets and wireless local loop subscriber units and base stations. the amplifier is biased to meet the requirements of linear modulation systems of w-cdma. the CMM3566-LC is packaged in a low-cost, space efficient, power package that provides excellent electrical sta- bility and low thermal resistance. the part requires minimal external circuitry for bias and matching to reduce space and cost. 3.45 to 3.5 ghz 7.0v, +24 dbm w-cdma power amplifier preliminary product information november 2000 (1 of 4) ground tab v g3 1 rf in 4 v g2 2 v g1 3 7 rf out/+v d3 8 rf out/+v d3 5 v d1 6 v d2 ground tab functional block diagram absolute maximum ratings parameter rating parameter rating parameter rating drain voltage (+v d ) +8 v* power dissipation 5 w operating temperature -30? to +90? drain current (i d ) 1.0 a thermal resistance 20?/w channel temperature 150? rf input power 0 dbm* storage temperature -65? to +150? soldering temperature 240? for 5 sec. dc gate voltage (-v g ) -4.0 v* bv gd 18 v recommended operating conditions parameter typ units parameter typ units drain voltage (+v d ) 7.0 volts operating temperature (pc board) -40 to +70 ? * max (+v d ) and (-v g ) under linear operation. max potential difference across the device at 1db gain compression point (2v d + |-v g |) not to exceed the minimum breakdown voltage (bv gd ) of +18v. application information the CMM3566-LC is a three stage amplifier that requires a positive and a negative supply voltages for proper operation. it is essential when turning on the device that the negative supply be applied before the positive supply. when turning the device off, the positive supply should be removed before the negative supply is removed. the CMM3566-LC can be operated over a range of supply voltages and bias currents. it is important that the maximum power dissipation specification for the package be observed at all times and that the maximum voltage across the device not be exceeded. circuit design considerations biasing three negative voltages are needed to set the bias current of the 3-stage gaas fet power amplifier. the first stage bias is controlled via vg1. the second stage bias is controlled via vg2. the output stage is controlled via vg3. the recommended divider networks for each gate bias shown in the schematic. the positive supply voltage is applied to pins 5, 6, 7 and 8. the negative volt- age supplies control the quiescent current of the device. the quies- cent current needs to be set at the level specified in order to get the guaranteed rf performances. negative bias voltages can also be used to control the gain, the output power and the operating current during operation of the device. matching circuits output matching circuit is required to achieve the output power and gain guaranteed. celeritek? recommenda- tion for the topology of the matching circuit is shown in the schematic diagram of the test circuit in this data sheet. in providing both the negative and positive bias voltages, it is important to provide adequate de-coupling between the rf signal and the dc voltages. inadequate de-coupling could result in low output power, low gain or oscillation. celeritek recommends the bias circuits shown in the evaluation circuit . ?continued on page 2
3236 scott boulevard, santa clara, california 95054 phone: (408) 986-5060 fax: (408) 986-5095 CMM3566-LC preliminary product information - nov ember parameter condition min typ max units frequency range 3.45 3.5 ghz gain @ digital power output 26 28.5 31 db gain variation over supply voltage 2 db/v over temperature 0.03 db/? harmonics* 2nd (pout = +22 to +26 dbm) -35 -30 dbc 3rd (pout = +22 to +26 dbm) and above -40 -35 dbc linear output power 2.7 mhz from carrier -43 -40 dbc/30 khz (pout = +22 dbm, data rate = 4.096mc/sec 5.25 mhz from carrier -50 -48 dbc/30 khz (pout = +22 dbm, data rate = 4.096mc/sec linear output power 2.7 mhz from carrier -38 -35 dbc/30 khz (pout = +24 dbm, data rate = 4.096mc/sec 5.25 mhz from carrier -47 -45 dbc/30 khz (pout = +24 dbm, data rate = 4.096mc/sec wideband noise 10 mhz bandwidth -68 dbc noise figure vdd = 7.0 v 5 db return loss input -10 -14 db return loss output -10 -14 db positive supply current (i d ) pout = +24 dbm 540 ma quiescent current (i q ) no rf 520 ma negative supply current (-i g ) includes external resistor divider 2.0 4.0 ma negative supply voltage (-v g ) into external resistor divider -0.3 -1.5 -3.0 v electrical characteristics unless otherwise specified, the following specifications are guaranteed at 3.45 ghz, room temperature with drain voltage (+v d ) = 7.0 v in celeritek test fixture. modulation when biased as specified, the CMM3566-LC will achieve the required adjacent channel response for the w-cdma linearity. celeritek tests each product under digital modulation to ensure compliance to system specifications. thermal 1. the copper pad on the backside of the CMM3566-LC must be soldered to the ground plane. ?continued from page 1 frequency s11 s21 s12 s22 (ghz) mag ang mag ang mag ang mag ang 0.6 0.646 136.623 2.393 20.992 0.002 -19.228 0.804 -23.817 0.8 0.659 54.979 1.283 17.015 0.003 -80.195 0.682 -89.402 1.0 0.732 -19.826 5.119 -67.405 0.004 -158.535 0.420 -138.407 1.2 0.778 -82.663 8.080 -171.314 0.005 132.866 0.382 -152.437 1.4 0.781 -140.684 10.458 93.318 0.005 67.738 0.533 150.599 1.6 0.751 155.653 12.110 -2.432 0.007 0.028 0.650 69.917 1.8 0.770 14.916 11.272 -176.757 0.006 -124.480 0.874 -61.986 2.0 0.770 11.996 11.158 -179.876 0.006 -126.766 0.880 -63.734 2.2 0.781 -40.876 11.715 106.441 0.007 173.071 0.911 -116.517 2.4 0.772 -81.765 15.438 32.091 0.008 128.121 0.877 -177.609 2.6 0.757 -121.242 21.302 -51.262 0.010 68.938 0.771 103.364 2.8 0.640 176.329 27.182 -150.627 0.011 -13.377 0.756 13.731 3.0 0.447 86.466 29.193 105.943 0.010 -79.627 0.690 -53.854 3.2 0.516 0.714 28.413 4.707 0.011 -137.593 0.471 -91.983 3.4 0.518 -69.213 25.542 -94.768 0.010 152.682 0.383 -99.415 3.6 0.131 -149.583 24.348 164.543 0.012 93.523 0.268 -121.022 3.8 0.423 -13.907 19.130 58.878 0.011 18.708 0.257 -98.953 4.0 0.578 -59.337 14.619 -37.638 0.008 -52.138 0.278 -134.978 s-parameters vdd = 7v, id 1 & 2 = 200, id 3 = 300 * the integrity of the input signal at an offset of 5.25 mhz has an adjacent channel performance of not greater than -52 dbc.
3236 scott boulevard santa clara, california 95054 phone: (408) 986-5060 fax: (408) 986-5095 CMM3566-LC preliminary product information - november 2000 (3 of 4) typical performance gain and return loss vs frequency linear output power vs frequency id & adjacent channel power vs output power (2.7 mhz from carrier) id & adjacent channel power vs output power (5.25 mhz from carrier)
3236 scott boulevard, santa clara, california 95054 phone: (408) 986-5060 fax: (408) 986-5095 celeritek reserves the right to make changes without further notice to any products herein. celeritek makes no warranty, repres entation or guarantee regarding the suitability of its products for any particular purpose, nor does celeritek assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters can and do vary in different applications. all operating parameters, including ?ypicals?must be validated for each customer application by customer? technical experts. celeritek doe s not convey any license under its patent rights nor the rights of others. celeritek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the celeritek p roduct could create a situation where personal injury or death may occur. should buyer purchase or use celeritek products for any such unintended or unauthorized application, buyer shall indemnify and hold celeritek and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that celeritek was negligent regarding the design or manufacture of the part. celeritek is a registered trademark of celeritek, inc. celeritek, inc. is an e qual opportunity/affirmative action employer. CMM3566-LC preliminary product information - november 2000 (4 of 4) ordering information the CMM3566-LC is available in a surface mount plastic lcc-8 package and devices are available in tube or tape and reel. part number for ordering package CMM3566-LC lcc-8 surface mount power package CMM3566-LC-000t lcc-8 surface mount power package in tape and reel pb-CMM3566-LC evaluation board with sma connectors for CMM3566-LC physical dimensions v g v dd r5 49.9 k ? c14 100 ? c8 0.01 ? c4 56 pf rf in (50 ? ) 1 2 3 4 8 7 6 5 CMM3566-LC rf out (50 ? ) c3 0.01 f c6 100 pf c7 100 pf c9 .01 ? c5 0.1 ? l1 27 nh l2 27 nh t4 105 ? 90 t3 61 ? 155 c17 0.9 pf c10* 100 pf v gg 1 c11 0.01 ? c12* 100 pf c1 0.01 f c2* 100 pf v gg 2 v gg 3 r2 1.5k r4 1.5k r3 427 ? r1 80 ? * = should be as close to leads as possible. recommended matching topology note: this schematic represents the topology of the matching circuit recommended by celeritek. evaluation board schematic board substrate: er = 3.38 thickness = 0.031 in.
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